Unit 1: Basic MOS Technology (Depletion mode MOS Transistor)

Depletion mode MOS Transistor

The depletion mode MOSFET shown as a N channel device (P channel is also available) in  is more usually made as a discrete component, i.e. a single transistor rather than IC form. In this device a thin layer of N type silicon is deposited just below the gate−insulating layer, and forms a conducting channel between source and drain.

 

Therefore when the gate source voltage V_GS is zero, current (in the form of free electrons) can flow between source and drain. Note that the gate is totally insulated from the channel by the layer of silicon dioxide. Now that a conducting channel is present the gate does not need to cover the full width between source and drain. Because the gate is totally insulated from the rest of the transistor this device, like other IGFETs, has a very high input resistance.

Operation of a Depletion Mode MOSFET

In the N channel device,  the gate is made negative with respect to the source, which has the effect of creating a depletion area, free from charge carriers, beneath the gate. This restricts the depth of the conducting channel, so increasing channel resistance and reducing current flow through the device.

 

Depletion mode MOSFETS are also available in which the gate extends the full width of the channel (from source to drain). In this case it is also possible to operate the transistor in enhancement mode. This is done by making the gate positive instead of negative. The positive voltage on the gate attracts more free electrons into the conducing channel, while at the same time repelling holes down into the P type substrate. The more positive the gate potential, the deeper, and lower resistance is the channel. Increasing positive bias therefore increases current flow. This useful depletion/enhancement version has the disadvantage that, as the gate area is increased, the gate capacitance is also larger than true depletion types. This can present difficulties at higher frequencies.

Circuit Symbols for Depletion Mode MOSFETs (IGFETs)

 

Notice the solid bar between source and drain, indicating the presence of a conducting channel.

Note: Making the gate more negative reduces conduction between source & drain In N channel devices, but increases conduction between source & drain In P channel devices.

Unit 1: Basic MOS Technology (Enhancement mode MOS Transistor)

P Channel Enhancement  mode MOS Transistor 

The p-channel MOSFET (PMOS) is manufactured similarly to the NMOS. Holes are the charge carriers in the p-type channel. PMOS was originally the dominant MOSFET, but was replaced by NMOS. NMOS can be manufactured smaller than PMOS and operate faster.

 

 

 

 

 

 

P-channel mosfets work in the same manner as an N-channel FET, but instead of controlling/controlled by positive voltage, they are controlled by negative voltage signals to the gate. They are off when the voltage to the gate is +V, and on when the voltage is negative, or zero.

P-channel FET’s are often physically smaller. They can not handle as much power, or as much voltage as most N-channel mosfets. Their On state resistance is usually considerably higher than N-channel FETS as well.

They’re used in switch mode power supplies to keep the ground at ground. If you used an N channel FET s, it would be above ground a certain voltage.

 

 

Unit 1: Basic MOS Technology (Enhancement mode MOS Transistor)

Enhancement and depletion mode MOS Transistor

Metal oxide semiconductor field effect transistor (MOSFET): It is a transistor for amplifying and switching electronic signals. It is also called Unipolar device because the current is produced by any one of the charge carrier either electrons or holes depending upon n channel or p channel. MOSFET is a four terminal device with source (S), drain (D), gate (G) and body (B) or substrate terminal. The body (B) of the MOSFET  is connected to the source terminal and is treated as 3 terminal device similar to FET. Actually these two terminals are internally short circuited and it appears like a 3 terminal device in electric diagrams.

This  diagram shows all the terminals and the gate is separated from the body by an insulating material. 

Electric circuit

Enhancement mode MOSFET:

The Metal Oxide Silicon FET (MOSFET) or Metal Oxide Silicon Transistor (M.O.S.T.) has an even higher input resistance (typically 10¹² to 10¹⁵ ohms) than that of the JFET. In the MOSFET device the gate is completely insulated from the rest of the transistor by a very thin layer of metal oxide (Silicon dioxide SiO₂). Hence the general name applied to any device of this type, is the IGFET or Insulated Gate FET.

 Construction of a N Channel Enhancement Mode MOSFET

The basic construction of a MOSFET is shown in diagram. The body or substrate of P type silicon is used, then two heavily doped N type regions are diffused into the upper surface, to form a pair of closely spaced strips.

A very thin (about 10⁻⁴ mm) layer of silicon dioxide is then evaporated onto the top surface forming an insulating layer. Parts of this layer are then etched away above the N type regions using a photographic mask to leave these regions uncovered. On top of the insulating layer, between the two N type regions, a layer of aluminium is deposited. This acts as the GATE electrode. Metal contacts are also deposited on the N type regions, which act as the SOURCE and DRAIN connectors

Enhancement Mode Operation.

The gate has a voltage applied to it that makes it positive with respect to the source. This causes holes in the P type layer close to the silicon dioxide layer beneath the gate to be repelled down into the P type substrate, and at the same time this positive potential on the gate attracts free electrons from the surrounding substrate material. These free electrons form a thin layer of charge carriers beneath the gate electrode (they can’t reach the gate because of the insulating silicon dioxide layer) bridging the gap between the heavily doped source and drain areas. This layer is sometimes called an “inversion layer” because applying the gate voltage has caused the P type material immediately under the gate to firstly become “intrinsic” (with hardly any charge carriers) and then an N type layer within the P type substrate.

Any further increase in the gate voltage attracts more charge carriers into the inversion layer, so reducing its resistance, and increasing current flow between source and drain. Reducing the gate source voltage reduces current flow. When the power is switched off, the area beneath the gate reverts to P type once more.

As well as the type described above, devices having N type substrates and P type (inversion layer) channels are also available. Operation is identical, but of course the polarity of the gate voltage is reversed.

This method of operation is called “ENHANCEMENT MODE” as the application of gate source voltage makes a conducting channel “grow”, therefore it enhances the channel. Other devices are available in which the application of a bias voltage reduces or “depletes” the conducting channel.

 Circuit Symbols for Enhancement Mode MOSFETs (IGFETs)

Threshold voltage : It  is abbreviated as Vth and is  defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. The formation of the inversion layer allows the flow of electrons through the gate-source junction.

For an enhancement-mode, n-channel MOSFET, the three operational modes are:

1. Cut-off , sub threshold or weak-inversion mode:

When V_GS < V_th:

where  is gate-to-source bias and  is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the Boltzmann distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.

In weak inversion the current varies exponentially with  as given approximately by:

,

where  = current at , the thermal voltage  and the slope factor n is given by

,

with  = capacitance of the depletion layer and  = capacitance of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once , but as channel length is reduced drain induced barrier lowering  introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage V_th for this mode is defined as the gate voltage at which a selected value of current I_D0 occurs, for example, I_D0 = 1 μA, which may not be the same V_th-value used in the equations for the following modes.

2. Triode mode or linear region (also known as the ohmic mode

When V_GS > V_th and V_DS < ( V_GS – V_th )

The transistor is turned on, and a channel has been created which allows current to flow between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. As here, the voltage between transistor gate and source ( V_GS) exceeds the threshold voltage(V_th), it is known as Overdrive Voltage. The current from drain to source is modeled as:

    

where  is the charge-carrier effective mobility,  is the gate width,  is the gate length and is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.

3. Saturation or active mode

When V_GS > V_th and V_DS > ( V_GS – V_th )

The switch is turned on, and a channel has been created, which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage, and modeled approximately as:

    

The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is:

,

where the combination V_ov = V_GS – V_th is called the overdrive voltage, and where V_DSsat = V_GS – V_th (which Sedra neglects) accounts for a small discontinuity in  which would otherwise appear at the transition between the triode and saturation regions.

Another key design parameter is the MOSFET output resistance r_out given by:

.

r_out is the inverse of g_DS where . I_D is the expression in saturation region.

If λ is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits.

As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by  velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in V_GS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In addition, the output current is affected by drain-induced barrier lowering of the threshold voltage.

Cross section of a MOSFET operating in the linear (Ohmic) region; strong inversion region present even near drain

Cross section of a MOSFET operating in the saturation (active) region; channel exhibits pinch-off near drain

Unit 1: BASIC MOS TECHNOLOGY (Integrated circuit’s era)

Integrated circuit’s era:

An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, or microchip) is an electronic circuit manufactured by  a process called lithography, or the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. Additional materials are deposited and patterned to form interconnections between semiconductor devices.

Integrated Circuits are almost used in all the equipments today for example like computers, mobile phones and digital home appliances

The integrated circuits can be  small scale integration, medium scale integration, large scale integration, very large scale integration.

The first integrated circuits contained only a few transistors. Called “small-scale integration” (SSI), digital circuits containing transistors numbering in the tens provided a few logic gates for example, while early linear ICs.  SSI circuits were crucial to early aerospace projects, and aerospace projects helped inspire development of the technology.

The next step in the development of integrated circuits, taken in the late 1960s, introduced devices which contained hundreds of transistors on each chip, called “medium-scale integration” (MSI). They were attractive economically because while they cost little more to produce than SSI devices, they allowed more complex systems to be produced using smaller circuit boards, less assembly work (because of fewer separate components), and a number of other advantages.

 minicomputers to use MSI (Medium Scale Integration)

Large-scale integration” (LSI) in the mid 1970s, with tens of thousands of transistors per chip. Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had under 4000 transistors. True LSI circuits, approaching 10,000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors.

The final step in the development process, starting in the 1980s and continuing through the present, was “very large-scale integration” (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009.

 With the introduction of Very Large Scale Integration (VLSI)

In 1986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips passed the million transistor mark in 1989 and the billion transistor mark in 2005. The trend continues largely unabated, with chips introduced in 2007 containing tens of billions of memory transistors.